Consider generating `iff` in always blocks

Verilog has syntax to allow writing things like:

`always @(clock iff someValue == 1) `

Which is a combination of an `sv.always` and `sv.if` block, which we frequently generate. As part of polishing the Verilog output we should decide if it is a good idea to fold these.

Start by tracing how the existing Verilog output handles always blocks alongside the sv.always and sv.if combination named in the issue. Determine whether folding them into Verilog's always ... iff syntax is appropriate, then document the decision and any required output changes.

Written by the indexing model from the issue text.