[HW] Enum aliasing in SV output

Currently, different enums with identical field names:
```mlir
hw.type_scope @fsm_enum_typedecls {
hw.typedecl @M2_state_t : !hw.enum
hw.typedecl @M1_state_t : !hw.enum
}
```

Will export as:
```sv
typedef enum {A, B} M2_state_t;
typedef enum {A, B} M1_state_t;
```
wherein enum values alias.

Enum values should be emitted with additional pre/suffixing of the enum type name to avoid this, e.g.:
```sv
typedef enum {M2_state_A, M2_state_B} M2_state_t;
typedef enum {M1_state_A, M1_state_B} M1_state_t;
```

Start by locating the SystemVerilog exporter handling hw.enum and inspect how enum field names are emitted. Reproduce the two-type example from the issue; done means generated SV gives each enum's values distinct names, such as M2_state_A and M1_state_A, without aliases.

Written by the indexing model from the issue text.