[PyCDE/CAPI] iverilog chokes on automatic logic
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Description
automatic logic can be circumvented by passing `--lowering-options=disallowLocalVariables` during `--export-verilog`.
For PyCDE, We'd want to be able to - at some point in the stack - to specify this variable. One point could be as a flag at the CAPI level: https://github.com/llvm/circt/blob/bc4c6874fd633f65966697e26ad41dbe9f16e82d/lib/Bindings/Python/CIRCTModule.cpp#L86-L90
As long as it is something which we can set when emitting RTL for `@cocotestbench` PyCDE runs.
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Research direction
Start in lib/Bindings/Python/CIRCTModule.cpp around the cited CAPI flag handling, then trace how --export-verilog lowering options reach RTL emission for PyCDE @cocotestbench runs. Determine an API path for setting disallowLocalVariables and verify that emitted RTL avoids automatic logic when used with iverilog.
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Assessment
- Tech stack
- cpp, python
- Domain
- compilers
- Issue type
- Feature
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 38/100