[ExportVerilog] Initial statement needs begin/end for single declaration

Input:
```mlir
hw.module private @Foo() -> (){
sv.initial {
%param_x = sv.localparam : i42 { value = 11: i42 }
}
}
```
`$ circt-opt -export-verilog` produces:
```verilog
module Foo();
initial
localparam [41:0] param_x = 42'd11;

endmodule
```

At least Verilator and Yosys produce a syntax error. When I added "begin" and "end" around initial statement, it parses.
```verilog
initial begin
localparam [41:0] param_x = 42'd11;
end
```

Start by reproducing the issue with the shown MLIR input and `circt-opt -export-verilog`, then inspect the ExportVerilog handling of `sv.initial`. Compare the generated output with Verilator or Yosys parsing; done means a single declaration is emitted inside `begin` and `end` and the result parses successfully.

Written by the indexing model from the issue text.