[PrepareForEmission] Temporaries are not spilled in a procedural region

Nobody has claimed this yet.

The following IR is derived from a test case of https://github.com/llvm/circt/pull/3116 which workarounded verilator hangs.
```mlir
hw.module @Verilator3405() -> () {
%state = sv.reg : !hw.inout
sv.initial {
%state_read = sv.read_inout %state : !hw.inout
%read = comb.extract %state_read from 0 : (i2) -> i1
%lhs = comb.or %read, %read, %read, %read, %read, %read, %read, %read, %read, %read, %read, %read : i1
%rhs = comb.or %read, %read, %read, %read, %read, %read, %read, %read, %read, %read, %read, %read : i1
%out = comb.concat %lhs, %rhs : i1, i1
sv.passign %state, %out : i2
}
}
```
With `circt-opt -export-verilog -lowering-options=disallowLocalVariables`, we get an expected result:
```
module Verilator3405();
wire _GEN;
wire _GEN_0;
reg [1:0] state;

assign _GEN_0 = state[0] | state[0] | state[0] | state[0] | state[0] | state[0] | state[0] | state[0] |
state[0] | state[0] | state[0] | state[0];
assign _GEN = state[0] | state[0] | state[0] | state[0] | state[0] | state[0] | state[0] | state[0] |
state[0] | state[0] | state[0] | state[0];
initial
state <= {_GEN_0, _GEN};
endmodule
```

`%lhs` and `%rhs` are spilled to temporary wires. On the other hand with `circt-opt -export-verilog`, the result is:
```
module Verilator3405();
reg [1:0] state;

initial
state <= {state[0] | state[0] | state[0] | state[0] | state[0] | state[0] | state[0] | state[0] |
state[0] | state[0] | state[0] | state[0], state[0] | state[0] | state[0] | state[0] |
state[0] | state[0] | state[0] | state[0] | state[0] | state[0] | state[0] | state[0]};
endmodule
```

I think it should be:
```verilog
initial begin
automatic logic _GEN_0 = state[0] | state[0] | state[0] | state[0] | state[0] | state[0] | state[0] | state[0] |
state[0] | state[0] | state[0] | state[0];
automatic logic _GEN = state[0] | state[0] | state[0] | state[0] | state[0] | state[0] | state[0] | state[0] |
state[0] | state[0] | state[0] | state[0];

state <= {_GEN_0, _GEN};
end
```

Start by reproducing the MLIR example with circt-opt using both default export and -lowering-options=disallowLocalVariables. Inspect the PrepareForEmission handling of temporaries in procedural regions. Done means the default export spills %lhs and %rhs to temporaries with valid procedural lifetime, matching the expected Verilog behavior.

Written by the indexing model from the issue text.