Circular logic not detected

Nobody has claimed this yet.

The following code:
```
module {
hw.module @foo() -> (o: i1) {
%0 = comb.parity %0 : i1
hw.output %0 : i1
}
}
```

is considered correct and produces the following Verilog output (using `circt-opt circular.mlir --export-verilog`):
```
module foo( // circular.mlir:2:3
output o);

wire _GEN = ^_GEN; // circular.mlir:3:10
assign o = _GEN; // circular.mlir:4:5
endmodule
```

analyzing this with Verilator gives the following error:
```
$ verilator circular.v --lint-only
%Error: circular.v:5:13: Wire inputs its own output, creating circular logic (wire x=x)
5 | wire _GEN = ^_GEN;
| ^
%Warning-UNOPTFLAT: circular.v:5:8: Signal unoptimizable: Feedback to clock or circular logic: 'foo._GEN'
5 | wire _GEN = ^_GEN;
| ^~~~
... For warning description see https://verilator.org/warn/UNOPTFLAT?v=4.222
... Use "/* verilator lint_off UNOPTFLAT */" and lint_on around source to disable this message.
circular.v:5:8: Example path: foo._GEN
circular.v:5:13: Example path: ASSIGNW
circular.v:5:8: Example path: foo._GEN
%Error: Exiting due to 1 error(s), 1 warning(s)
```

in other words, this simple circular logic is not detected by the tools.

On a side note: `firtool` seems to hang up on this simple example and other circular examples

Reproduce the example in circular.mlir with circt-opt --export-verilog and compare it with Verilator's circular-logic diagnostic. Also check the reported firtool hang on this and other circular examples. Done means the tools detect or otherwise reject the circular logic instead of accepting the input and emitting self-referential Verilog.

Written by the indexing model from the issue text.