[SV] Generate case/if blocks

I need to emit verilog which selects a module to instantiate based on a module parameter. I think the only way to do that is a generate block like:

  generate
  begin
    if (__INST_HIER == "top.child[0]")
    begin
      Child_dst2_width8_pipedepth3 impl(.clk(clk));
    end
    else if (__INST_HIER == "top.child[1]")
    begin
      Child_dst2_width8_pipedepth4 impl(.clk(clk));
    end
    else if (__INST_HIER == "top.genchild[0]")
    begin
      Child_dst3_width32_pipedepth4 impl(.clk(clk));
    end
    else if (__INST_HIER == "top.bar")
    begin
      Child_dst3_width32_pipedepth4 impl(.clk(clk));
    end
    else
      $fatal(1, "%m: Could not find specialized module for %s", __INST_HIER);
  end
  endgenerate

(I just learned that I can use a case statement instead of ifs, but same difference.)

Is there some other way for me to achieve the desired result which we currently support? If not, I'll have to go about adding support for generate blocks, yes? (Or am I just not seeing it?) Should I use the existing sv.if or sv.case ops (inside of the generate op Block). They only support integer conditions (so they're synthesizable). Should I make them more generic?

I'm pretty sure the answers to my questions are 'no', 'correct', ('you're not blind'), and 'yes', respectively. The SV dialect is intended to be more AST/syntactic than logical, right? I wanted to check before I put in the work.

Start by reading the existing sv.if and sv.case operations and the generate operation's Block, as named in the issue. Determine whether their current integer-only conditions can express the requested module-selection form; done means the generate-block conditional structure can represent the shown Verilog pattern.