[ExportVerilog] Reuse output ports if possible

Consider following IR (this kind of IR is frequently used to express FIRRTL's inout ports):
```mlir
hw.module @Foo(%x: i8) -> (y: i8, z: i8) {
%.z.output = sv.wire : !hw.inout
%0 = sv.read_inout %.z.output : !hw.inout
sv.assign %.z.output, %x : i8
hw.output %0, %0 : i8, i8
}
```
`circt-opt -export-verilog`:
```verilog
module Foo( // foo.mlir:1:1
input [7:0] x,
output [7:0] y,
z);

wire [7:0] _z_output; // foo.mlir:2:18

assign _z_output = x; // foo.mlir:4:5
assign y = _z_output; // foo.mlir:3:10, :5:5
assign z = _z_output; // foo.mlir:3:10, :5:5
endmodule
```

Ideally we don't have to create temporary wires for output ports, e.g:
```verilog
module Foo( // foo.mlir:1:1
input [7:0] x,
output [7:0] y,
z);

assign z = x; // foo.mlir:4:5
assign y = x; // foo.mlir:3:10, :5:5
endmodule

Start by reproducing the issue with the shown IR and the circt-opt -export-verilog entry point. Trace how the ExportVerilog path handles sv.wire values read from output ports, then verify that the generated Verilog removes the temporary wire while preserving the two output assignments shown in the request.

Written by the indexing model from the issue text.