Discrepancy between behavioral simulation and post-implementation simulation/ hardware execution

Hello,

I am using the most current version of CIRCT and I am having issues getting even some "basic" RTL to work properly. The behavioral simulation in Vivado 2021.2 is working correctly, but the post-implementation timing simulation shows incorrect behavior. I even tried the sample dot.mlir code from the circt/integration_test/Dialect/Handshake/ folder and using the driver code provided I get the same results. Below are screenshots of simulating the RTL generated from dot.mlir using the provided lowering commands:

Behavioral simulation:

Post-implementation timing simulation:

When I programmed the FPGA, the hardware was effectively not working. In both cases, it seems the RTL halts executing very early on.

Doing some debugging, I noticed in both the example code and my design, the multiplication module (arith_multi) is combinational. I do not know if this is the expected behavior but tracing things, the output of the multiplier is never computed in post-implementation simulation or in actual hardware (checked using an ILA). To make matters worse, the operation is mapped to a DSP with the clock tied to 0 so it never completes any computation.

Below are screenshots of the multi modules in both RTL and Synthesis schematic:

RTL:

Synthesized

Any insights if I am doing anything wrong would be appreciated.

Start with circt/integration_test/Dialect/Handshake/dot.mlir and reproduce the reported lowering and simulation flow in Vivado 2021.2. Inspect the generated arith_multi RTL and its synthesized DSP connection, comparing behavioral simulation, post-implementation timing simulation, and ILA observations. Done means explaining the discrepancy and identifying a correction that makes the multiplier compute on hardware.

Written by the indexing model from the issue text.