[SV] Miss-complication by reordering side-effect ops

```mlir
hw.module @Foo(%clock:i1, %a:i8, %b:i8) {
%reg = sv.reg : !hw.inout
%fd = hw.constant 0x80000002 : i32
sv.always posedge %clock {
sv.bpassign %reg, %a : i8
%x = sv.read_inout %reg : !hw.inout
sv.bpassign %reg, %b : i8
sv.fwrite %fd, "%d"(%x) : i8
}
}
```

Current output:
```verilog
module Foo(
input clock,
input [7:0] a,
b);

reg [7:0] reg_0;

always @(posedge clock) begin
reg_0 = a;
reg_0 = b;
$fwrite(32'h80000002, "%d", reg_0);
end // always @(posedge)
endmodule
```

This is incorrect because the value of `a` should be printed. I guess we have to create a temporary register if we can't use `automatic`.

Start by reproducing the MLIR example with the SystemVerilog operations sv.bpassign, sv.read_inout, and sv.fwrite, then trace the SystemVerilog emission for this always block. Done means the generated Verilog preserves the value assigned from a before the later assignment from b, so the fwrite prints a.

Written by the indexing model from the issue text.