[comb] Missing Optimization to Build Reduction Ops

We are missing an optimization to build reduction ops when possible. Consider the following which is doing `b[0] | b[1]`:

```mlir
module {
hw.module @Foo(%a: i1, %b: i2) -> (c: i1) {
%0 = comb.extract %b from 1 : (i2) -> i1
%1 = comb.extract %b from 0 : (i2) -> i1
%2 = comb.or %0, %1 {sv.namehint = "_b"} : i1
hw.output %2 : i1
}
}
```

This produces:
```verilog
module Foo(
input a,
input [1:0] b,
output c);

assign c = b[1] | b[0];
endmodule
```

It would be better to produce (`comb.icmp ne 0`):
```verilog
assign c = |b;
```

This optimization should be possible for any of `comb.or`, `comb.and`, and `comb.xor`.

Start from the comb.or, comb.and, and comb.xor operations shown in the MLIR example and trace how they become Verilog. Compare the current b[1] | b[0] output with the requested reduction form, then verify that equivalent reductions for all three operations produce the expected Verilog.

Written by the indexing model from the issue text.