[SV] Add support for `sv.case` items to be variables instead of only binary constants

SystemVerilog case statements in CIRCT look like this:
https://github.com/llvm/circt/blob/main/test/Conversion/ExportVerilog/sv-dialect.mlir#L299

Each `case` in a `sv.case` is a binary 4-value constant. In SystemVerilog, you can put `logic` signals directly into the case items to be matched of the case statement, which adds a lot of flexibility.

It would also be cool to propagate constants from variables into the case statement, at least in trivial cases (e.g. a variable assigned directly to a `hw.constant`).

This is an important set of features for [ROHD](https://github.com/intel/rohd) to generate SystemVerilog using CIRCT.

Start with the sv.case examples in test/Conversion/ExportVerilog/sv-dialect.mlir to understand the current binary-constant case items. Define completion as allowing logic signals as case items and covering trivial propagation from variables assigned directly to hw.constant, with corresponding test coverage.

Written by the indexing model from the issue text.