[HW] Add support for generator expressions

#2701, #2703 introduces support for using HW module parameters in `seq, comb` operations as well as support for parametric arrays.

To be able to do something meaningful with this, a next step could be to add a `generate` operation to the HW dialect, wherein we can use control flow operations to describe our parametric hardware.
This would then be accompanied by an elaboration step that is invoked upon module instantiation. By doing this in CIRCT (as opposed to emitting SystemVerilog `generate` structures), we'll be able to leverage existing RTL dialect optimizations and transformations/inlining/....

To kick off a discussion, one possible implementation is to implement a `hw.generate` operation that defines a region. Internally, `SCF`
or `affine` dialect operations could be used as the elaboration language. The main challenge with this is to be able to use our `#hw.param.decl.ref<"...">` attributes as values accepted by the verifiers of these operations, such as the following:

```mlir
hw.module @accumulate(%vec : !hw.array<#hw.param.decl.ref<"N"> x i32>) -> (out: i32) {
%tmp = sv.wire : i32
hw.generate {
%first = hw.array_get %vec[0] : i32
%ub = hw.param.value i32 = #hw.param.decl.ref<"N">
%sum = scf.for %iv = 1 to %ub step 1 iter_args(%sum_iter = %first) -> (i32) {
%v = hw.array_get %vec[%iv] : i32
%partial_sum = comb.add %sum_iter, %v
scf.yield %partial_sum : i32
}
sv.assign %tmp, %sum : i32
}
hw.output %tmp : i32
}
```

Start by reading the context from issues #2701 and #2703, then review the proposed HW dialect operation and its interaction with SCF or affine operations. Use the example generator region to understand the intended elaboration at module instantiation; the work is complete only when the design and implementation approach for parameter values, control flow, and elaboration are agreed.

Written by the indexing model from the issue text.