[firtool][ExportVerilog] Inline CSE'd Expressions

Nobody has claimed this yet.

Currently, `firtool` isn't inlining expressions which would help Verilog readability. This is coming from CSE'd expressions which are then not re-inlined.

Consider the following:

```scala
circuit Foo :
module Foo :
input a : UInt<1>
input b : UInt<1>
input c : UInt<1>
input d : UInt<1>
output e : UInt<1>
output f : UInt<1>

node _x_T = or(a, b)
node _x_T_1 = or(c, d)
node x = or(_x_T, _x_T_1)
node _y_T = or(a, b)
node _y_T_1 = and(c, d)
node y = or(_y_T, _y_T_1)
e <= x
f <= y
```

With `firtool`, this produces:

```verilog
module Foo( // Foo.fir:2:10
input a, b, c, d,
output e, f);

wire _x_T = a | b; // Foo.fir:10:17
assign e = _x_T | c | d; // Foo.fir:2:10, :12:14
assign f = _x_T | c & d; // Foo.fir:2:10, :14:19, :15:14
endmodule
```

The SFC produces:

```verilog
module Foo(
input a,
input b,
input c,
input d,
output e,
output f
);
assign e = a | b | (c | d);
assign f = a | b | c & d;
endmodule
```

In this situation, it would be better to not emit the CSE'd temporary `a | b` and instead emit it inline.

Use the FIRRTL example in the issue as the reproduction and start by tracing firtool's ExportVerilog flow, focusing on how CSE'd expressions become emitted temporaries. Done means the shared a | b expression is inlined in the generated Verilog rather than emitted as a temporary, while the shown outputs remain correct.

Written by the indexing model from the issue text.