[FIRRTL] Bitwidth conventions for artihmetic ops

Nobody has claimed this yet.

`firtool` bit extends each operand to the destination type. This seems to differ from `firrtl` output.
The output is semantically correct, but this might be a verilog output quality issue.
So, if a multiplication produces 3 bit result, then the input operands are extended to 3 bits.
This is the standard assumption for `HW` dialect, https://github.com/llvm/circt/blob/main/lib/Conversion/FIRRTLToHW/LowerToHW.cpp#L3005

Input `fir`
```python
circuit MyModule :

module MyModule :
input in1: UInt<1>
input in2: UInt<2>
output out: UInt<3>

out <= mul(in1, in2)
```
`firtool` output
``` verilog
module MyModule(
input in1,
input [1:0] in2,
output [2:0] out);
assign out = {2'h0, in1} * {1'h0, in2};
endmodule
```
`firrtl` output
```verilog
module MyModule(
input in1,
input [1:0] in2,
output [2:0] out
);
assign out = in1 * in2;
endmodule
```

Start with the FIRRTL-to-HW lowering logic in lib/Conversion/FIRRTLToHW/LowerToHW.cpp around the referenced line. Compare the generated Verilog operand extensions with FIRRTL behavior for arithmetic operations such as the supplied multiplication example. Done means the intended bitwidth convention is established and the resulting output behavior is validated by an appropriate regression.

Written by the indexing model from the issue text.