[HW][SV] Unpacked Struct
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HW
Verilog/SystemVerilog
- Dominant language
- C++
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Description
I want to try unpacked structs for bundle type lowering of FIRRTL but seems currently not supported.
Considering this issue https://github.com/llvm/circt/issues/389, it might be better to add unpacked struct type to sv dialect though.
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First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start by reading the FIRRTL bundle type lowering discussion in this issue and the related CIRCT issue #389, then inspect how the SV dialect represents struct types. Define what support for unpacked struct types should cover and verify that bundle lowering produces the expected SystemVerilog representation.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- cpp
- Domain
- compilers
- Issue type
- Feature
- Difficulty
- 5/5
- Estimated time
- Over a week
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 25/100