[ExportVerilog] Omit bitwidth of constant array index
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ExportVerilog
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Description
hw.module @Foo(%a: !hw.array<1xi1>) -> (b: i1) {
%false = hw.constant false
%0 = hw.array_get %a[%false] : !hw.array<1xi1>
hw.output %0 : i1
}
module Foo( // foo.fir:2:10
input [0:0] a,
output b);
assign b = a[1'h0]; // foo.fir:2:10, :5:12
endmodule
I'm not 100% sure it is always legal but can't we just emit assign b = a[0] ?
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Research direction
Start with the ExportVerilog path for the constant-indexed hw.array_get shown in the issue, using the provided MLIR input to reproduce the generated SystemVerilog. Verify whether the index width is required, then confirm that the completed output uses a widthless constant index such as a[0] and remains valid for the example.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- cpp
- Domain
- compilers
- Issue type
- Bug
- Difficulty
- 3/5
- Estimated time
- 1-2 days
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 48/100