[ExportVerilog] Type scope emission in split outputs mode

Currently type scopes are all copied to each output file:
For example this mlir, `firtool -split-verilog` creates two files "UseA.sv" and "UseB.sv".
```mlir
hw.type_scope @scope_A { hw.typedecl @T_A : i1 }
hw.module @UseA(%source: !hw.typealias<@scope_A::@T_A, i1>) {}
hw.type_scope @scope_B { hw.typedecl @T_B : i1 }
hw.module @UseB(%source: !hw.typealias<@scope_B::@T_B, i1>) {}
```

Followings are current outputs.
* UseA.sv
```sv
typedef logic T_A;
module UseA( // hoge.mlir:2:1
input T_A source);

endmodule

typedef logic T_B;
```
* UseB.sv
```sv
typedef logic T_A;
typedef logic T_B;
module UseB( // hoge.mlir:4:1
input T_B source);

endmodule
```

It is better not to emit all type decls but emit subsets of types used by emitted module.

Start at the ExportVerilog split outputs implementation and reproduce the issue with the MLIR example using firtool -split-verilog. Done means each generated output file contains only the type declarations used by its emitted module, rather than all type declarations.

Written by the indexing model from the issue text.