[ExportVerilog] Consider to cache results of `isExpressionUnableToInline`
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ExportVerilog
- Dominant language
- C++
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Description
`isExpressionUnableToInline(op)` checks all users to determine the given operation is allowed to emit inline.
I haven't done proper profiling but it might be possible to speed up ExportVerilog by cacheing the result of `isExpressionUnableToInline`.
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Research direction
Locate isExpressionUnableToInline(op) in the ExportVerilog implementation and inspect how it traverses users. Profile ExportVerilog before changing behavior, then evaluate whether caching the result is correct and beneficial. Done means inlineability decisions remain unchanged and the measured export performance improves.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- cpp
- Domain
- compilers
- Issue type
- Refactor
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 45/100