[ExportVerilog] CSE of Assert Action Block Temporaries trips VCS Lint

Outlining of expressions from concurrent assertion action blocks is tripping a VCS lint error. Something like the following seems to show the issue. Here, an expression in the action block is shared between two statements. This then gets CSE'd.

```mlir
hw.module @Foo(%clock: i1, %a: i1, %b: i1) -> (b: i1) {
%0 = comb.or %a, %b : i1
sv.assert.concurrent posedge %clock, %0 label "hello" message "world"(%a) : i1
hw.output %0 : i1
}
```

This produces (`firtool Baz.mlir`):
```verilog
module Foo( // Baz.mlir:1:1
input clock, a, b,
output b_0);

wire _T = a | b; // Baz.mlir:2:8
hello: assert property (@(posedge clock) _T) else $error("world", a); // Baz.mlir:3:3
assign b_0 = _T; // Baz.mlir:4:3
endmodule
```

VCS then complains along the lines of "non-sampled variable `_T` is used in the action block of assertion". I'm not sure if this is actually a problem.