[ExportVerilog] Unnecessary temporary for bind

When a bind (well, the instance for the bind) is emitted, expressions are spilled to wires. The assignment of the expression to these wires is often spilled, leading to:
```
wire foo;
wire _T;
assign _T = expr;
assign foo = _T;
```
This extra assignment is really ugly and unnecessary.

Start in the ExportVerilog implementation at the code that emits bind instances and spills expressions to wires. Trace how the wire assignment is generated; done means a bind expression is emitted without the redundant intermediate wire assignment while preserving the necessary connection.

Written by the indexing model from the issue text.