[ExportVerilog][Comb] Improve namings of temporary wires
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Description
Currently, most of comb operations is not handled in inferStructuralNameForTemporary.
https://github.com/llvm/circt/blob/e3f2c4eec39146127e56b8ba5894515d909674af/lib/Conversion/ExportVerilog/ExportVerilog.cpp#L858-L860
It would be arguable how much we should do namings for temporaries but it would be good to implement some trivial patterns to improve verilog readablity.
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Research direction
Start in lib/Conversion/ExportVerilog/ExportVerilog.cpp at inferStructuralNameForTemporary, especially the referenced lines handling combinational operations. Review which trivial comb-operation patterns are currently omitted and implement naming improvements for them. Done means generated Verilog uses more readable names for those temporary wires.
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Assessment
- Tech stack
- cpp
- Domain
- compilers
- Issue type
- Feature
- Difficulty
- 3/5
- Estimated time
- 1-2 days
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 48/100