[ExportVerilog] Remove temporary for aggregate outputs

For the following fir,
```scala
module Bar:
input a: {clock: Clock, reset: UInt<1>},
output b: {clock: Clock, reset: UInt<1>}
b <= a
```
In aggregate preservation mode, we currently emit this:
```verilog
module Bar( // foo.fir:2:10
input struct packed {logic clock; logic reset; } a,
output struct packed {logic clock; logic reset; } b);

wire struct packed {logic clock; logic reset; } _b_output;

assign _b_output.clock = a.clock;
assign _b_output.reset = a.reset;
assign b = _b_output; // foo.fir:2:10
endmodule
```

It is better not to emit temporary `_b_output`, like:
```verilog
module Bar( // foo.fir:2:10
input struct packed {logic clock; logic reset; } a,
output struct packed {logic clock; logic reset; } b);

assign b.clock = a.clock; // foo.fir:5:7
assign b.reset = a.reset; // foo.fir:5:7
endmodule
```

Start with the ExportVerilog implementation that handles aggregate-preservation assignments, using the FIR and Verilog examples in this issue as the expected behavior. Done means generated aggregate outputs assign directly to their fields without emitting the temporary _b_output value.

Written by the indexing model from the issue text.