[ExportVerilog] Improve concurrency approach for performance

Nobody has claimed this yet.

We use a parallel foreach loop for the bulk of the work in export verilog which works reasonably well, except when you have a large module near the end of the circuit. The issue is that you get one worker handling the long talk large module because it gets kicked off late.

To help this, we should get an approximate side for each module in the early prepare pass, and sort the "modules to be processed" vector by size (so largest modules are at the beginning). This will reduce the amount of long tail work one a single core.

This pattern would be useful to generalize to other passes as well, but ExportVerilog seems the most egregious and already has multiple passes.

Start by locating the ExportVerilog implementation, its early prepare pass, and the parallel foreach over modules. Inspect how the modules-to-be-processed vector is built and identify where approximate module sizes can be computed. Done means processing order uses those sizes so the largest modules begin earlier and the long-tail single-worker work is reduced.

Written by the indexing model from the issue text.