[LowerToHW] Use type decl for Bundle type lowering

If there are large structs in ports, we might get long lines. For example(from FPU.fir),
```mlir
; circt-opt %s -export-verilog
hw.module @Long(%clock: i1, %io_cp_req_bits: !hw.struct) {
}
```
will generate
```verilog
module Long( // foo.mlir:1:1
input clock,
input struct packed {logic [4:0] cmd; logic ldst; logic wen; logic ren1; logic ren2; logic ren3; logic swap12; logic swap23; logic single; logic fromint; logic toint; logic fastpipe; logic fma; logic div; logic sqrt; logic wflags; logic [2:0] rm; logic [1:0] typ; logic [64:0] in1; logic [64:0] in2; logic [64:0] in3; } io_cp_req_bits);

endmodule
```

This looks not good so we may consider to use type decl at module scope.

Reproduce the example from FPU.fir with `circt-opt %s -export-verilog` and compare the generated module port declaration for `@Long`. Investigate the lowering path responsible for Bundle ports; done means large struct types are declared at module scope rather than emitted as long inline Verilog port types.

Written by the indexing model from the issue text.