[LowerToHW] Define Behavior for Multiple Circuits

Nobody has claimed this yet.

Currently, if you compile multiple FIRRTL circuits, only one of them gets lowered. We need to define a behavior here for how this should work and what the resulting HW representation is. Consider the following:

```mlir
module {
firrtl.circuit "Foo" {
firrtl.module @Foo(in %a: !firrtl.uint<1>, out %b: !firrtl.uint<1>) {
firrtl.connect %b, %a : !firrtl.uint<1>, !firrtl.uint<1>
}
}
firrtl.circuit "Bar" {
firrtl.module @Bar(in %a: !firrtl.uint<1>, out %b: !firrtl.uint<1>) {
firrtl.connect %b, %a : !firrtl.uint<1>, !firrtl.uint<1>
}
}
}
```

This produces, after `LowerToHW`:
```mlir
module {
firrtl.circuit "Bar" {
firrtl.module @Bar(in %a: !firrtl.uint<1>, out %b: !firrtl.uint<1>) {
firrtl.connect %b, %a : !firrtl.uint<1>, !firrtl.uint<1>
}
}
hw.module @Foo(%a: i1) -> (b: i1) {
hw.output %a : i1
}
}
```

If allowed to continue after this, eventually `ExportVerilog` will print an error because it doesn't know how to handle a `firrtl.circuit`.

I can think of two behaviors here:

1. This should produce a flat list of modules.
2. (Likely what we need) This should lower each to two lists of modules in a `hw.namespace`-guarded region.

Start by tracing the LowerToHW entry point and the later ExportVerilog handling of firrtl.circuit. Compare the flat-module and hw.namespace approaches, determine the intended representation for multiple circuits, and define completion as consistent lowering of every circuit without leaving unsupported firrtl.circuit operations for ExportVerilog.

Written by the indexing model from the issue text.