[ExportVerilog] Add support for bit swapping idiom

ExportVerilog emits a concat that bitswaps like this:

```
thing = {io_in1[0], io_in1[1], io_in1[2], io_in1[3], io_in1[4]...}
```

but there are better idioms for this. We could generate them directly, and we may want to introduce a comb op for bitswapping.

Start by tracing the ExportVerilog handling of concatenations like the shown io_in1 bit sequence. Determine which bit-swapping idiom should be emitted and whether a dedicated comb operation is needed; done means the exporter handles this pattern with the agreed idiom and covers the behavior with appropriate validation.

Written by the indexing model from the issue text.