[FIRRTL] Preserve vectors in lowering

Nobody has claimed this yet.

Currently, LowerTypes flattens all aggregated types. Therefore, this firrrtl:
```firrtl
circuit Foo:
module Foo:
input clock: Clock
input a: UInt<1>[2][2]
output b: UInt<1>[2][2]

reg r: UInt<1>[2][2], clock
r <= a
b <= r
```
is converted into
```verilog
module Foo( // foo.fir:2:10
input clock, a_0_0, a_0_1, a_1_0, a_1_1,
output b_0_0, b_0_1, b_1_0, b_1_1);

reg r_0_0; // foo.fir:7:5
reg r_0_1; // foo.fir:7:5
reg r_1_0; // foo.fir:7:5
reg r_1_1; // foo.fir:7:5

always @(posedge clock) begin // foo.fir:8:7
r_0_0 <= a_0_0; // foo.fir:8:7
r_0_1 <= a_0_1; // foo.fir:8:7
r_1_0 <= a_1_0; // foo.fir:8:7
r_1_1 <= a_1_1; // foo.fir:8:7
end // always @(posedge)

assign b_0_0 = r_0_0; // foo.fir:2:10
assign b_0_1 = r_0_1; // foo.fir:2:10
assign b_1_0 = r_1_0; // foo.fir:2:10
assign b_1_1 = r_1_1; // foo.fir:2:10
endmodule
```
but preferably the following is better in terms of readability and simulation costs:
```verilog
module Foo( // foo.fir:2:10
input clock,
input [1:0][1:0] a,
output [1:0][1:0] b);

reg [1:0][1:0] r; // foo.fir:7:5

always @(posedge clock) // foo.fir:8:7
r <= a; // foo.fir:8:7
assign b = r; // foo.fir:2:10
endmodule
```
It is also better for bundles to be lowered into `sv.interface` but in the issue, I'd like to limit the scope to preserve vectors.
I think base vector types(N-dim array not containing bundle) at leafs can be lowered directly.

For this, there are following tasks across several passes:

- [x] #2131

- [x] LowerToHW
Initialize random value for arrays
https://github.com/llvm/circt/pull/2143

- [x] ExpandWhens
https://github.com/llvm/circt/pull/2286

- [ ] LowerTypes
Change to do expand connections instead of lowering them into individual aggregates.
https://github.com/llvm/circt/pull/2318

Maybe outdated but related to:
* https://github.com/llvm/circt/issues/123
* https://llvm.discourse.group/t/firrtl-aggregate-types-discussion/1806/23

Start with the LowerTypes pass, using the FIRRTL vector example in the issue and the referenced LowerToHW and ExpandWhens work as context. The change is complete when base N-dimensional vector types at leaves are preserved through lowering and connections are expanded rather than lowered into individual aggregates.

Written by the indexing model from the issue text.