[ESI] Update PipelineStage lowering to target CIRCT ops instead of System Verilog implementation

Nobody has claimed this yet.

Right now, the ESI lowering for PipelineStage currently declares external modules: https://github.com/llvm/circt/blob/3042bb18987fb2e8717c5cdd47de4e674570c15e/lib/Dialect/ESI/ESIPasses.cpp#L183-L187

The handcoded SystemVerilog module is here: https://github.com/llvm/circt/blob/3042bb18987fb2e8717c5cdd47de4e674570c15e/include/circt/Dialect/ESI/ESIPrimitives.sv#L7-L38

That external module is instantiated and wired up in the lowering pattern that handles PipelineStage: https://github.com/llvm/circt/blob/3042bb18987fb2e8717c5cdd47de4e674570c15e/lib/Dialect/ESI/ESIPasses.cpp#L888

It would be a nice enhancement to replace the `hw.module.extern` with a CIRCT `hw.module` that implements the same behavior. We should have all the necessary ops in the HW, Comb, and SV dialects, including support for parameterizing the module by bitwidth. If this implementation is useful, perhaps down the road we could pull PipelineStage and this lowering out of the ESI dialect.

Start with the PipelineStage lowering in lib/Dialect/ESI/ESIPasses.cpp, especially the external-module declarations near line 183 and the lowering pattern near line 888. Compare these with include/circt/Dialect/ESI/ESIPrimitives.sv to preserve the existing behavior, then replace the hw.module.extern with a parameterized hw.module using the HW, Comb, and SV dialects.

Written by the indexing model from the issue text.