[ExportVerilog] Verilator width warning about array_get

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```mlir
hw.module @Foo(%array: !hw.array<4xi6>, %c: i1, %d: i2) -> (b: i6) {
%c0_i2 = hw.constant 0 : i2
%0 = comb.mux %c, %c0_i2, %d : i2
%1 = hw.array_get %array[%0] : !hw.array<4xi6>
hw.output %1 : i6
}
```
will be lowered into
```verilog
module Foo( // foo.mlir:1:1
input [3:0][5:0] array,
input c,
input [1:0] d,
output [5:0] b);

assign b = array[c ? 2'h0 : d]; // foo.mlir:2:13, :3:14, :4:12, :5:5
endmodule
```

Verilator produces the following warnings
```
%Warning-WIDTH: a.sv:7:22: Operator COND expects 32 or 3 bits on the Conditional True, but Conditional True's CONST '2'h0' generates 2 bits.
: ... In instance Foo
7 | assign b = array[c ? 2'h0 : d];
| ^
... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
%Warning-WIDTH: a.sv:7:22: Operator COND expects 32 or 3 bits on the Conditional False, but Conditional False's VARREF 'd' generates 2 bits.
: ... In instance Foo
7 | assign b = array[c ? 2'h0 : d];
| ^
```

Start by reproducing the shown MLIR example through the ExportVerilog lowering and running the generated Verilog with Verilator. Trace how hw.array_get forms its index expression; done means the generated output preserves the example's behavior without the reported width warnings.

Written by the indexing model from the issue text.