Tabs in Verilog emission

Verilog emitter uses tabs in some places to align comments. Example

In port list:

In assign statements:

Tab size/behavior heavily depend on the editor / viewer and in general don't guaranty alignment.
We use spaces for indentation and alignment in most of the cases.
Using tabs in just one particular case and in the in the middle of the line complicates handling of the code.

How to reproduce

The following FIRRTL program

circuit top_mod:
  module top_mod:
    input a: UInt<42>
    output b: UInt
    output bb: UInt
    output bbb: UInt
    output bbbb: UInt
    b <= tail(a, 40)
    bb <= tail(a, 3)
    bbb <= tail(a, 2)
    bbbb <= tail(a, 1)

Compiled with firtool --lower-to-hw --infer-widths --imconstprop --lowering-options=disallowPackedArrays,emittedLineLength=8192 --mlir-timing --verilog -o=$VFILE2 produces this code:

module top_mod(	// a_top_mod.fir:2:10
  input  [41:0] a,
  output [1:0]  b,
  output [38:0] bb,
  output [39:0] bbb,
  output [40:0] bbbb);

  assign b = a[1:0];	// a_top_mod.fir:2:10, :8:10
  assign bb = a[38:0];	// a_top_mod.fir:2:10, :9:11
  assign bbb = a[39:0];	// a_top_mod.fir:2:10, :10:12
  assign bbbb = a[40:0];	// a_top_mod.fir:2:10, :11:13
endmodule

Start by tracing the firtool Verilog emission path responsible for port-list and assign-statement comments, using the reproducer and generated Verilog in this issue. Verify the output with the supplied FIRRTL program and confirm that tabs are removed while comment alignment remains consistent.