llvm / llvm/circt

[Parameterized modules] Add a `hw.int<T>` type

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@lattner is already working on this.

Since Oct 5, 2021.

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Description

The next step in the journey for parameterized modules is to add parameterized types. The first one that makes sense to add is a parameterized integer type. Adding this is straight-forward now that parameter expressions are attributes, it roughly looks like:

1) Add the type. I suggest we make the width always be pinned to 32-bits to make the syntax cleaner and to line up with (non-System)Verilog better.
2) Assert that the parameter expressions are only-valid expressions at construction time.
3) We need operation verification to check that operations in a module only refer to valid parameterized types. The delta with step 2 is that we need to make sure that referenced parameters are correctly defined and typed within the module, e.g. reject:

```
hw.module @foo() {
someop: !hw.int // invalid type in foo module because p2 isn't defined here.
}
```

4) We need to handle parameter name legalization. This is not at all straight-forward given our current design for name legalization, because renaming a parameter would require changing the types of arbitrary operations, something that is a bit crazy. The right way to fix it is to complete Issue #1708, making the renaming completely a problem within the ExportVerilog pass.

5) [x] The problem with this is that we need to change HWExportModuleHierarchy around. I'll discuss this with richard.

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