[PrettifyVerilog] Transform (some) array_create/get pairs into cases

As discussed in the design meeting it would make sense to lower certain array_create/get pairs into case statements (potentially in an always_comb block):

1. When the expression feeding the elements is large, complicated, and single use it would make sense to generate case statements.
2. When multiple array_get's exists that use the same index condition it makes sense to fold them together into a single larger case. It is possible that this is just a "case folding" peephole that triggers after the first one.

We need to be careful not to go overboard here though, because the array_create syntax is nice for simple inline expressions. The example in the rationale docs should stay inline for example.

Read the linked design-meeting discussion and the array operation rationale in docs/RationaleHW-SV.md first. Then locate the PrettifyVerilog implementation and its existing tests; completion should selectively lower suitable array_create/get pairs while keeping simple inline expressions, including the rationale example, unchanged.