[HW] Parameterized Modules, step #2: using expressions

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As a follow on to Issue #1489 (step 1), we need to start building the "expression language" for parameters (e.g. "foo+42 * (bar&1)". Some basic requirements:

- Parameters need to be refer to the declarations set up in step 1: #1489.
- They need to be referrable from types (so we can have a bitvector whose width is "n").
- We also have to keep parameters and values separate: parameters are a metaprogramming system, and while it is ok for the value domain to use parameters, it isn't ok for parameters to depend on values.
- Parameters have a expanded/different type system (incl strings, etc) than comb logic does.

Because these have to be referenced from types, they must be attributes. I think we should add something like the following two attributes:

- `hw.param.ref "someparam" : whatevertype`: a reference to a named parameter in the current context. I think that referring to them by name is fine.
- `hw.param.binop "add" lhs, rhs : whatevertype`: we need a grammar of simple expression operators, we can learn from AffineExpr here.

We need to define what the operators are, but can start with some simple and obvious ones like add/sub/mul to get started. We would also use IntegerAttr in the expression grammar.

To start using these, we should:

1) take the recently added "sv.localparam" and change it (back, sorry my advice was bad in the PR review) to taking an attribute as an operand instead of taking an SSA value. This operator because a way of forming a named parameter within a context, projecting it from the parameter domain (attributes) into the SSA value domain.

2) add a new "hw.param" op which returns (e.g.) an integer SSA value and takes an attribute. It is the same as `sv.localparam` but is for the "anonymous" usecase, where you want to just reference "n" on the right side of a comb.add or whatever.

3) extend `hw.instance` to be able to specify parameters to parameterized modules, this is an attribute list.

We should then add ExportVerilog support for this whole stack.

Step #⁠3 will be to start setting up the parameterized type system.

Start with Issue #1489 and the existing sv.localparam and hw.instance operations to understand the parameter declarations and current operand handling. Define the hw.param.ref and hw.param.binop attributes, update sv.localparam and add hw.param, extend hw.instance parameter lists, then add ExportVerilog support for the complete stack and cover the basic operators such as add, sub, and mul.

Written by the indexing model from the issue text.