[SV] Make InterfaceInstanceOp more like InterfaceOp

SystemVerilog dialect's modeling of `InterfaceInstanceOp` is a bit of an odd duck. _Module instantiations_ in FIRRTL and HW dialects are both function-like, but `InterfaceInstanceOp` works differently. `InterfaceInstanceOp` currently has a return type of the interface type with a symbol back to the interface declaration.

The problem is that interfaces in SystemVerilog can be treated just like modules and instantiated. Something like::

```verilog
MyInterface myInterface(
.a(a),
.b(b)
);
```

The current approach doesn't really capture this use case well. I'd like to see some unification around "instantiation" of modules and interfaces so that things like emitting binds (which works for either interface instances or module instances) then isn't having to be handled totally differently.

See terse initial suggestion from @darthscsi here: https://github.com/llvm/circt/pull/1432#discussion_r674333321.

Start by reading the InterfaceInstanceOp and InterfaceOp definitions, then compare module instantiations in the FIRRTL and HW dialects. Review the terse proposal in the linked pull request discussion. Done means interface and module instantiations share a model that supports common bind emission without separate handling.

Written by the indexing model from the issue text.