[SV] Remove duplication of non-"wire-equivalent"/"free" operations in PrettifyVerilog

https://github.com/llvm/circt/blob/2594d38300a40c1ce718e56359b9885468fc35c4/lib/Dialect/SV/Transforms/PrettifyVerilog.cpp#L93

This function duplicates operations and is run on unary operations which create logic. We can't rely on SV synthesis tools to de-duplicate the logic introduced here. Only operations which get synthesized to wires ("free" or "wire-equivalent") are candidates for duplication.

Open lib/Dialect/SV/Transforms/PrettifyVerilog.cpp at line 93 and inspect the operation-duplication function and its handling of unary operations. Confirm that only operations synthesized to wires, including “free” or “wire-equivalent” operations, remain duplication candidates; logic-producing operations should no longer be duplicated.

Written by the indexing model from the issue text.