[MooreToCore] Bugs breaking SV compilation: Ternary logic, DisableIff, and ClockingBlock

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# CIRCT Regression Testcase: P0 SVA & RTL Triad

This testcase isolates a cluster of three tightly coupled P0 failures that collectively block any real-world SystemVerilog RTL + SVA flow from compiling through CIRCT. The target encompasses 4-state ternary legalization failures, concurrent assertion `disable iff` omissions, and implicit default clocking inference failures.

### 1. Minimal Working Testcase (`p0_triad_test.sv`)

This self-contained, LRM-compliant module triggers all three bugs simultaneously with minimal LOC.

```systemverilog
// Target Compiler: circt-verilog (Slang/Moore)
// Bug A: arith.select with !moore.l1
// Bug B: DisableIff in concurrent assertion
// Bug C: implicit clock inference / ClockingBlock
module p0_triad_test (
input logic clk,
input logic rst_n,
input logic sel,
input logic a,
input logic b,
output logic y
);
// Bug A trigger: ternary on logic signals
assign y = sel ? a : b;

// Bug C trigger: default clocking block
default clocking cb @(posedge clk); endclocking

// Bug B + C trigger: disable iff with implicit clock inherited from 'cb'
p0: assert property (disable iff (!rst_n) a |=> b);
p1: assert property (disable iff (!rst_n) a |=> y);
endmodule
```

### 2. CIRCT Paths & Bug Locations

Based on the AST lowering and dialect conversion pipelines, the fixes must be implemented in the following locations:

* **Bug A (`arith.select`):** `circt/lib/Conversion/MooreToCore/LowerToHW.cpp`. The `ConvertMooreToCore` pass marks `arith.select` as illegal but lacks a conversion pattern when operands are `!moore.l1`.
* **Bug B (`DisableIff`):** Slang AST frontend importer (typically `circt/lib/ImportSystemVerilog/` or `circt/lib/Dialect/Moore/`). The `concurrent_assertion_statement` visitor encounters the `DisableIff` slang AST node and falls through to an unhandled exception.
* **Bug C (`ClockingBlock` / Inference):** The slang-to-moore frontend elaboration is missing AST visitors for `slang::ast::ClockingBlockSymbol` (LRM §14). Consequently, clock inference for sequences (LRM §16.16) fails.

### 3. Expected MLIR Output

Upon successful frontend lowering and dialect conversion, CIRCT should produce the following IR structure (or equivalent `hw` / `seq` lowering):

```mlir
// Expected after slang->Moore frontend import:
moore.module @p0_triad_test(...) {
// Bug A: Ternary assignment gracefully handled
%cond = moore.conversion %sel : !moore.l1 -> i1
%mux_res = "moore.conditional"(%cond, %a, %b) : (i1, !moore.l1, !moore.l1) -> !moore.l1
moore.assign %y, %mux_res : !moore.l1

// Bug B & C: Clocking block parsed, implicitly passed, disable iff modeled
%clk_ev = moore.clock_event posedge %clk
%rst_cond = moore.not %rst_n
moore.assert_property @p0 (%clk_ev, disable_iff %rst_cond) {
moore.implication_non_overlapped %a, %b
}
}
```

### 4. Reproduction Command & Diagnostics

**Command:**
```bash
circt-verilog p0_triad_test.sv -o /dev/null
```

**Expected Failing Diagnostics (Current CIRCT HEAD):**
```text
p0_triad_test.sv:13:5: error: unsupported module member: ClockingBlock
p0_triad_test.sv:16:26: error: unsupported expression: DisableIff
p0_triad_test.sv:16:9: error: sequence has no explicit clocking event and one cannot be inferred from context
failed to legalize operation 'arith.select' that was explicitly marked illegal:
%4 = "arith.select"(%arg0, %3, %2) : (i1, !moore.l1, !moore.l1) -> !moore.l1
```

### 5. Fix Sketch

* **For Bug A (`LowerToHW.cpp`):** Implement an `OpConversionPattern` (or its Moore equivalent) that matches `!moore.l1` types. The pattern should convert the 4-state operands by extracting their 2-state boolean value and X-state mask, emitting underlying `comb.mux` or `hw.mux` operations to reflect LRM Table 11-2 four-state multiplexing behavior.
* **For Bug B & C (Slang Importer):** Extend the frontend AST visitor to handle `slang::ast::ClockingBlockSymbol`. Register the parsed clocking event into the current module's context. Update the concurrent assertion visitor to intercept `DisableIff` AST nodes, mapping them into an explicit asynchronous reset condition operand on the resulting `moore.assert` MLIR op. If a sequence lacks an explicit clock, the visitor must fall back to the registered default clocking context before emitting the IR.

Start by running circt-verilog p0_triad_test.sv -o /dev/null and inspect LowerToHW.cpp plus the Slang importer under circt/lib/ImportSystemVerilog/ and circt/lib/Dialect/Moore/. Trace the arith.select, DisableIff, and ClockingBlock diagnostics separately. Done means the testcase compiles and the resulting IR represents four-state ternary selection, disable iff, and default-clock inference as described.

Written by the indexing model from the issue text.