[LLHD] Add an SSA-style value-to-signal conversion operation

Nobody has claimed this yet.

We currently emit code like the following in a lot of places:
```mlir
%0 = llhd.const [...]
%1 = llhd.const [...] : !llhd.time
%signal = llhd.sig "foo" %0
llhd.drv %signal, %value after %1
```
The intent is to get a signal which has exactly one driver, which continuously drives a value onto the signal with some delay. We should add a new operation to the LLHD dialect, maybe calling it `llhd.output`, that represents this pattern in a more SSA-friendly way:
```mlir
%0 = llhd.const [...] : !llhd.time
%signal = llhd.output "foo" %value after %0
```
Then update the `RTLToLLHD` conversion to use the buffer where it currently materializes a signal.

Start by locating the LLHD dialect operation definitions and the RTLToLLHD conversion. Compare the repeated llhd.sig and llhd.drv pattern with the proposed SSA-style operation, then update the conversion to use it; done means the conversion emits the new value-to-signal form while preserving the value and delay semantics.

Written by the indexing model from the issue text.