chipsalliance / chipsalliance/usb2
[DOC] Add additional architectural description in HUB control chapter addressing the comments.
- Dominant language
- VHDL
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- 1
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- 6
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- 4d 13h
- Merged PRs (30d)
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Description
Should we have some more specifics on why the USB hub records are sufficient? (as in more details on the hub RAM config and why that covers all conditions)
_Originally posted by @bharatpillilli in https://github.com/chipsalliance/usb2/pull/3#discussion_r3846497082_
Contributor guide
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Research direction
Locate the HUB control chapter and review the surrounding USB hub architecture and RAM configuration descriptions. Use the referenced comment as the starting context, then document why the hub records and RAM configuration cover all conditions; done means the chapter addresses those points with sufficient architectural detail.
Written by the indexing model from the issue text.
Assessment
- Domain
- documentation
- Issue type
- Documentation
- Difficulty
- 3/5
- Estimated time
- 1-2 days
- Activity status
- Active
- Clarity
- Mostly clear
- Newbie friendliness
- 55/100