Guard DEV1 CSR against unsupported AXI transfer sizes

## Problem

The dedicated DEV1 CSR path in `src/integration/rtl/ip_xxx_3511_hs_mem_compound_wrapper.sv` forwards every AHB `HSIZE` and address alignment from `axi_to_ahb`. The downstream VHDL `usb_ahb_slave` has no size or byte-enable input and writes all 32 bits of `reg_wdata` while returning OKAY.

A byte, halfword, or unaligned AXI write can therefore overwrite the entire 32-bit CSR instead of only the requested bytes.

Originally reported in PR #18: https://github.com/chipsalliance/usb2/pull/18#discussion_r3994164523

## Recommended approach

Add an adapter on the dedicated DEV1 CSR path that admits aligned 32-bit accesses only. Unsupported transfers must not select or write the VHDL CSR target and must return a protocol-compliant error response. Alternatively, add explicit size and byte-enable support to the CSR implementation if partial CSR writes are required.

## Acceptance criteria

- Aligned 32-bit reads and writes preserve current behavior.
- Byte, halfword, oversized, and unaligned accesses have no CSR side effects.
- Unsupported accesses return an error response that is compliant on both the AHB and AXI sides.
- Add directed tests covering supported and rejected transfer profiles.

Trace the dedicated DEV1 CSR path in src/integration/rtl/ip_xxx_3511_hs_mem_compound_wrapper.sv, starting at axi_to_ahb and the downstream usb_ahb_slave target. Check how transfer size, alignment, selection, and error responses pass between AXI and AHB. Done means aligned 32-bit accesses retain current behavior, unsupported accesses have no CSR side effects, both interfaces return compliant errors, and directed tests cover accepted and rejected profiles.

Written by the indexing model from the issue text.