chipsalliance / chipsalliance/rocket-chip
Request to decouple PerfCounterIO's increment width from RetireWidth
- Dominant language
- Scala
- Stars
- 3.9k
- Forks
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- Avg merge
- 5d 13m
- Merged PRs (30d)
- 1
Description
Sorry for probably introducing the original hack, but I'd like to make a request to decouple the PerfCounterIO event's width from the retireWidth.
https://github.com/ucb-bar/rocket-chip/blob/master/src/main/scala/rocket/CSR.scala#L152
I would like a RocketCoreParams field that will let me choose what I want the event increment width to be.
My use-case is that a processor's issueWidth is likely to be wider than its retireWidth. Separating out different issue ports to separate events in not tenable, since software may want to save/restore counter state on a fine granularity. Even for coarse performance analysis on FPGAs, 29 hpm counters can run out fast.
Does this seem reasonable?
Contributor guide
Research direction
Start at src/main/scala/rocket/CSR.scala#L152 and trace how PerfCounterIO's event width is derived from retireWidth and how RocketCoreParams is used. Define the configurable increment-width behavior independently of retireWidth, then verify that the issue's wider-issue-width use case and counter save/restore granularity are supported.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- scala
- Domain
- embedded-iot
- Issue type
- Feature
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 35/100