1R1W memories have fantasy behavior and are "doomed to succeed"

https://github.com/ucb-bar/rocket-chip/blob/master/vsim/vlsi_mem_gen:

assign R0_data = ram[reg_R0_addr]; (generated by line 103)

This means that the R0_data output is auto-updated each cycle with the contents of the memory at that address, regardless of whether a valid read was initiated on the previous cycle. For this reason, simulation may work correctly in situations where the actual surrounding logic is incorrect. This kind of issue is likely to create simulation mismatches when hardened rams are instantiated.