ASIdBits parameter always set to 0

Hello,

I am using the Chipyard framework to simulate tests on the BOOM processor. I am trying to change the ASID field of the RISC-V SATP CSR to something other than 0, to verify that multiple OS contexts can run on BOOM simultaneously. I edited the dirty.S Supervisor-mode assembly test case to set the SATP register's ASID field to 1 (see code snippet 1). I verified that the test case works and the correct data is being written to the SATP register (see code snippet 2). However, the SATP register's ASID field is being continuously overwritten by 0, due to the asIdBits parameter being equal to 0 (see code snippet 3). The asIdBits parameter is based on the ASIdBits parameter (see code snippet 4), which only appears to have a default declaration (see code snippet 5). Is it intentional that asIdBits is always 0? Is there a proper way to override this so that an OS running can have multiple contexts?

Snippet 1: Code from dirty.S test case. The four lines market with '# added' were added by me to set the ASID field of the SATP register to 1.
```
# Turn on VM
li a0, (SATP_MODE & ~(SATP_MODE<<1)) * SATP_MODE_SV39
la a1, page_table_1
srl a1, a1, RISCV_PGSHIFT
or a1, a1, a0
li a2, 1 # added
li a3, 44 # added
sll a2, a2, a3 # added
or a1, a1, a2 # added
csrw satp, a1
sfence.vma
```

Snippet 2: Code from CSR.scala. I added the print statement to check if the modified test case data was getting to the SATP register. The print output was as expected, with ASID = 0001.
```
when (decoded_addr(CSRs.satp)) {
if (usingVM) {
val new_satp = wdata.asTypeOf(new PTBR())
when (new_satp.mode.isOneOf(satp_valid_modes.map(_.U))) {
reg_satp.mode := new_satp.mode & satp_valid_modes.reduce(_|_).U
reg_satp.ppn := new_satp.ppn(ppnBits-1,0)
if (asIdBits > 0) reg_satp.asid := new_satp.asid(asIdBits-1,0)
printf("new satp: wdata %x, when cast to PTBR: mode %x, ppn %x, asid%x\n", wdata, new_satp.mode, new_satp.ppn, new_satp.asid)
}
}
}
```

Snippet 3: Code from CSR.scala. I added the print statement, which is continuously printed during simulation run, indicating that asIdBits = 0.
```
if (!(asIdBits > 0)) {
printf("asIdBits is <= 0, so reg_satp.asid = 0\n")
reg_satp.asid := 0.U
reg_vsatp.asid := 0.U
}
```

Snippet 4: Code from BaseTile.scala. asIdBits is based on a parameter called ASIdBits.
`def asIdBits: Int = p(ASIdBits)`

Snippet 5: Code from TLB.scala. ASIdBits is set by default to 0, and not overridden anywhere in the rocket-chip directory.
`case object ASIdBits extends Field[Int](0)`

Start with ASIdBits in TLB.scala and trace p(ASIdBits) through BaseTile.scala into CSR.scala. Compare the default with the configuration used by Chipyard/BOOM, then inspect the dirty.S simulation that writes SATP. Done means the intended override path is established and the ASID value is no longer continuously forced to zero.

Written by the indexing model from the issue text.