Simulation times out when executing WFI with questa simulator

Hi guys,

I am trying to run chipyard design (https://github.com/ucb-bar/chipyard) with questa simulator. I compiled and optimized the design and my optimized top name is "opt".

This is my vsim command:
vsim "+permissive" -do "run -all; quit" -l vsim.log -gblso chipyard/riscv-tools/lib/libfesvr.so -gblso chipyard/riscv-tools/lib/libdramsim.so -gblso chipyard/riscv-tools/lib/libriscv.so -c opt +verbose "+dramsim" "+dramsim_ini_dir=chipyard/generators/testchipip/src/main/resources/dramsim2_ini" "+max-cycles=10000000" "+loadmem=chipyard/riscv-tools/riscv-tests/build/isa/rv64ui-p-simple" "+permissive-off" +rv64ui-p-simple

I added "+" sign to the binary file to be compatible with questa simulator, and then I removed it inside the C files (SimDRAM.cc and SimTSI.cc) and I made sure the argument is read in a proper format.

Although, the emulator doesn't show any errors, the simulation hangs and times out when reaching the WFI instruction (10500073). Please find below part of the generated transcript with some debugging messages inserted:
`# run -all
== Loading device model file 'chipyard/generators/testchipip/src/main/resources/dramsim2_ini/DDR3_micron_64M_8B_x4_sg15.ini' ==
== Loading system model file 'chipyard/generators/testchipip/src/main/resources/dramsim2_ini/system.ini' ==
===== MemorySystem 0 =====
CH. 0 TOTAL_STORAGE : 4096MB | 1 Ranks | 16 Devices per rank
DRAMSim2 Clock Frequency =666666666Hz, CPU Clock Frequency=500000000Hz
C0: 19 [1] pc=[0000000000010000] W[r10=0000000000010000][1] R[r 0=0000000000000000] R[r 0=0000000000000000] inst=[00000517] DASM(00000517)
C0: 20 [1] pc=[0000000000010004] W[r10=0000000000010040][1] R[r10=0000000000010000] R[r 0=0000000000000000] inst=[04050513] DASM(04050513)
C0: 21 [1] pc=[0000000000010008] W[r 0=0000000000000000][1] R[r10=0000000000010040] R[r 0=0000000000000000] inst=[30551073] DASM(30551073)
C0: 26 [1] pc=[000000000001000c] W[r 5=800000000094112d][1] R[r 0=0000000000000000] R[r 0=0000000000000000] inst=[301022f3] DASM(301022f3)
C0: 29 [1] pc=[0000000000010010] W[r 5=ffffe00000000025][1] R[r 5=800000000094112d] R[r 0=0000000000000000] inst=[4122d293] DASM(4122d293)
C0: 30 [1] pc=[0000000000010014] W[r 5=0000000000000001][1] R[r 5=ffffe00000000025] R[r 0=0000000000000000] inst=[0012f293] DASM(0012f293)
C0: 31 [1] pc=[0000000000010018] W[r 0=0000000000000000][0] R[r 5=0000000000000001] R[r 0=0000000000000000] inst=[00028863] DASM(00028863)
C0: 32 [1] pc=[000000000001001c] W[r 0=0000000000000020][1] R[r 0=0000000000000000] R[r 0=0000000000000000] inst=[30301073] DASM(30301073)
C0: 37 [1] pc=[0000000000010020] W[r10=0000000000000222][1] R[r 0=0000000000000000] R[r 0=0000000000000000] inst=[22200513] DASM(22200513)
C0: 38 [1] pc=[0000000000010024] W[r 0=0000000000000022][1] R[r10=0000000000000222] R[r 0=0000000000000000] inst=[34453073] DASM(34453073)
C0: 43 [1] pc=[0000000000010028] W[r10=0000000000000008][1] R[r 0=0000000000000000] R[r 0=0000000000000000] inst=[00800513] DASM(00800513)
C0: 44 [1] pc=[000000000001002c] W[r 0=d8fff19cff0a22a8][1] R[r10=0000000000000008] R[r 0=0000000000000000] inst=[30451073] DASM(30451073)
C0: 49 [1] pc=[0000000000010030] W[r 0=0000000a00001800][1] R[r10=0000000000000008] R[r 0=0000000000000000] inst=[30052073] DASM(30052073)
C0: 54 [1] pc=[0000000000010034] W[r 0=0000000000000000][0] R[r 0=0000000000000000] R[r 0=0000000000000000] inst=[10500073] DASM(10500073)

[UART] UART0 is here (stdin/stdout).
The number of arguments are 21
arg 0 - LoadDesign
arg 1 - +permissive
arg 2 - -do
arg 3 - run -all; quit
arg 4 - -l
arg 5 - vsim.log
arg 6 - -gblso
arg 7 - chipyard/riscv-tools/lib/libfesvr.so
arg 8 - -gblso
arg 9 - chipyard/riscv-tools/lib/libdramsim.so
arg 10 - -gblso
arg 11 - chipyard/riscv-tools/lib/libriscv.so
arg 12 - -c
arg 13 - opt
arg 14 - +verbose
arg 15 - +dramsim
arg 16 - +dramsim_ini_dir=chipyard/generators/testchipip/src/main/resources/dramsim2_ini
arg 17 - +max-cycles=10000000
arg 18 - +loadmem=chipyard/riscv-tools/riscv-tests/build/isa/rv64ui-p-simple
arg 19 - +permissive-off
arg 20 - rv64ui-p-simple
arg 21 - (null)
DRAMSim is enabled
DRAMSim INI directory set to: chipyard/generators/testchipip/src/main/resources/dramsim2_ini
Loadmem file set to: chipyard/riscv-tools/riscv-tests/build/isa/rv64ui-p-simple
Iteration 0: Attempting to load ELF: chipyard/riscv-tools/riscv-tests/build/isa/rv64ui-p-simple
Iteration 0: Attempting to load ELF: chipyard/riscv-tools/riscv-tests/build/isa/rv64ui-p-simple
Iteration 0: ELF loaded successfully!
Symbol: , Address: 0x0
Symbol: $xrv64i2p1_m2p0_a2p1_f2p2_d2p2_zicsr2p0_zifencei2p0_zmmul1p0, Address: 0x80000000
Symbol: _end, Address: 0x80002000
Symbol: _start, Address: 0x80000000
Symbol: begin_signature, Address: 0x80002000
Symbol: cczODynM.o, Address: 0x0
Symbol: end_signature, Address: 0x80002000
Symbol: fromhost, Address: 0x80001040
Symbol: handle_exception, Address: 0x80000038
Symbol: other_exception, Address: 0x80000038
Symbol: reset_vector, Address: 0x80000050
Symbol: tohost, Address: 0x80001000
Symbol: trap_vector, Address: 0x80000004
Symbol: write_tohost, Address: 0x8000003c
Iteration 0: Loadmem bool value = 1
Memory initialized successfully for chip_id 0 with parameters:
Creating new testchip_tsi_t instance for chip_id: 0
[DEBUG] testchip_tsi_t constructor called
[DEBUG] testchip_tsi_t constructor finished
tsi_tick: chip_id = 0, out_valid = 0, in_ready = 1
HTIF START CALLED
ENTERED THE START HTIF IF BLOCK
tsi_tick: Updated signals - in_valid = 0, in_bits = -148800480, out_ready = 1
tsi_tick: chip_id = 0, done = 0, exit_code = 0
tsi_tick: chip_id = 0, out_valid = 0, in_ready = 1
[DEBUG] write_chunk called with taddr = 0x80000000, nbytes = 444
[DEBUG] is_loadmem is true, calling load_mem_write
[DEBUG] write_chunk finished
[DEBUG] write_chunk called with taddr = 0x80001000, nbytes = 72
[DEBUG] is_loadmem is true, calling load_mem_write
[DEBUG] write_chunk finished
tohost_addr: 80001000
fromhost_addr: 80001040
HTIF RESET CALLED
[DEBUG] reset function called
[DEBUG] write_hart0_msip is true, calling tsi_t::reset
[DEBUG] write_chunk called with taddr = 0x2000000, nbytes = 4
[DEBUG] is_loadmem is false, flushing cache and writing
[DEBUG] flush_cache_lines called with taddr = 0x2000000, nbytes = 4
[DEBUG] No cache flush address set, skipping
[DEBUG] write_chunk finished
[DEBUG] reset function finished
[DEBUG] read_chunk called with taddr = 0x80001000, nbytes = 8
[DEBUG] is_loadmem is false, flushing cache and reading
[DEBUG] flush_cache_lines called with taddr = 0x80001000, nbytes = 8
[DEBUG] No cache flush address set, skipping
tsi_tick: Updated signals - in_valid = 1, in_bits = 1, out_ready = 1
tsi_tick: chip_id = 0, done = 0, exit_code = 0
tsi_tick: chip_id = 0, out_valid = 0, in_ready = 1
tsi_tick: Updated signals - in_valid = 1, in_bits = 2000000, out_ready = 1
tsi_tick: chip_id = 0, done = 0, exit_code = 0
tsi_tick: chip_id = 0, out_valid = 0, in_ready = 1
tsi_tick: Updated signals - in_valid = 1, in_bits = 0, out_ready = 1
tsi_tick: chip_id = 0, done = 0, exit_code = 0
tsi_tick: chip_id = 0, out_valid = 0, in_ready = 1
tsi_tick: Updated signals - in_valid = 1, in_bits = 0, out_ready = 1
tsi_tick: chip_id = 0, done = 0, exit_code = 0
-2147483646*** / *** (timeout) after 10000001 simulation cycles
** Fatal: Assertion error.
Time: 10000000500 ps Scope: TestDriver File: chipyard/generated-src/chipyard.harness.TestHarness.RocketConfig/gen-collateral/TestDriver.v Line: 151
** Note: $finish : chipyard/generated-src/chipyard.harness.TestHarness.RocketConfig/gen-collateral/TestDriver.v(151)
Time: 10000000500 ps Iteration: 1 Instance: /TestDriver
End time: 14:07:38 on Mar 06,2025, Elapsed time: 0:07:07
Errors: 1, Warnings: 0`

Notice that lines below keep on repeating till the simulation times out:
tsi_tick: Updated signals - in_valid = 1, in_bits = 2000000, out_ready = 1
tsi_tick: chip_id = 0, done = 0, exit_code = 0
tsi_tick: chip_id = 0, out_valid = 0, in_ready = 1

What could be the problem here? please advise.
Thanks in advance

Reproduce the supplied Questa `vsim` command and confirm where execution reaches WFI before the repeated `tsi_tick` messages and TestDriver.v timeout. Read SimDRAM.cc, SimTSI.cc, and the generated TestDriver.v assertion at line 151, then trace the HTIF/TSI signals to determine why the test never completes. Done means the cause is identified and the simulation completes without the timeout.

Written by the indexing model from the issue text.