Async register not needed in IntSyncCrossingSource?

I was looking at the path from the external interrupts to the PLIC. In the IntSyncCrossingSink, it passes through a three stage synchronizer cell. That cell is marked as with the name Primitive which I am replacing with a 3-stage synchronizer standard cell.

What I am concerned about is why in the IntSyncCrossingSource, there is another async register that is added?

Taken from `generators/rocket-chip/src/main/scala/interrupts/Crossing.scala`.
> class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule
> {
> val node = IntSyncSourceNode(alreadyRegistered)
>
> lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl)
>
> class Impl extends LazyModuleImp(this) {
> def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0)
> override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}"
> (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
> **out.sync := AsyncResetReg(Cat(in.reverse)).asBools**
> }
> }

This extra flop creates a path of interrupts in -> flop -> 3 stage sync -> other logic

This is messing with our timing checks, the first flop it sees is a regular flop so it believes it needs to meeting timing on that path. What's the reason for adding this flop?

Start in generators/rocket-chip/src/main/scala/interrupts/Crossing.scala and compare IntSyncCrossingSource with IntSyncCrossingSink, focusing on the AsyncResetReg and three-stage synchronizer path. Trace the timing intent and existing handling of alreadyRegistered; done means the need for the extra register is documented or the issue is resolved with appropriate validation.

Written by the indexing model from the issue text.