AXIToTL component can‘t support axi outstanding？

Hello @terpstra @aswaterman , we conducted secondary development based on Rocket and developed a coprocessor that supports the RVV instruction set. We will convert AXI interface to Tile link interface by AXIToTL component, because its external memory access interface is AXI4 interface.
However，we found that if an outstanding transmission is initiated (multiple consecutive ar commands with the same ID), AXIToTL will only issue one tilelink read request until the data is returned, and then issue the next tilelink read request, which will seriously affect the memory access performance of RVV.
How can I fix this performance point? Have you encountered similar problems before？I tried to modify the FIFO type of TLFIFOFixer module and found that allFIFO and allVolatile types can issue multiple tilelink commands, but there will be an assertion failure which is "channel re-used a source ID(connected at myrocc.scala)".

Start by tracing the AXIToTL component and the TLFIFOFixer configuration involved in outstanding reads, then inspect the source-ID assertion connected at myrocc.scala. Reproduce multiple consecutive AXI read commands with the same ID and compare the FIFO modes; done means outstanding requests improve without triggering the source-ID reuse assertion.

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