RoCC Core Clock Gating Bug

**Type of issue**: bug report | feature request | other enhancement
Bug report

**Impact**: no functional change | API addition (no impact on existing code) | API modification | unknown
Functional change

**Development Phase**: request | proposal
Request
**Other information**

The current clock gating logic inside the Rocket Cores do not take into account the RoCC busy signal. As a result, there are times when the RoCC request is being responded to but the core clock gating kicks in and doesn't allow the response to be registered inside the core. This results in the core hanging.

My suggestion here is to change clock_en_reg to also include the io.rocc.busy signal inside RocketCore.scala. I can put up a pull request for this bug fix if required.

**What is the current behavior?**
Clock gate enable gets deasserted while RoCC is busy.

**What is the expected behavior?**
Clock gate logic needs to account for RoCC custom instructions before gating the core clock.

Waveform below shows the current bug.

Start in RocketCore.scala by locating clock_en_reg and tracing how io.rocc.busy participates in the core clock-gating decision. Use the reported waveform and current behavior as the reproduction guide; done means the clock-gating logic no longer deasserts while a RoCC request is being responded to, so the core does not hang.

Written by the indexing model from the issue text.