Cannot find *behav_srams.v` in generated verilog files

I want to add a new CPU variant to the LiteX project, which requires a `*behav_srams.v` file based on the sample code already in LiteX, as well as a verilog file that includes all the CPU code.

However, when generating Verilog code with the current version of Rocket Chip, there is no `*behav_srams.v` file, and all RTL modules are located in separate files.

Maybe I can use the `cat` command to aggregate all the modules into a single file. But with the missing *behav_srams.v file, there's not much I can do.

Start by reproducing Verilog generation with the current Rocket Chip version and compare its separate RTL output with the LiteX sample code. Determine how the missing behav_srams.v file and combined CPU RTL are expected to be produced; done means the generated output supports the requested LiteX CPU variant.

Written by the indexing model from the issue text.