Chisel generates invalid nesting of always blocks and/or initializations.

When running yosys -p "read_verilog -sv generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.sv"
on my newly generated System Verilog code, after finally extending Yosys for the new syntax it didn't know yet
it correctly points out that this code Chisel generates isn't valid.

always @(posedge clock) begin
automatic logic _T_2; // src/main/scala/chisel3/util/Decoupled.scala:52:35
automatic logic _T_5; // src/main/scala/chisel3/util/Decoupled.scala:52:35

Is there a flag for telling Chisel to not do initializations within always blocks or do I have to hack Yosys so
that it moves initialization out of such always blocks?

In other words.
Who's going to fix this?
Rocket Chip/Chisel or Yosys?

Reproduce the generated SystemVerilog with the reported `yosys -p "read_verilog -sv ..."` command and inspect the declarations traced to `src/main/scala/chisel3/util/Decoupled.scala:52:35`. Determine whether the generated nesting is invalid and whether the issue belongs in Rocket Chip/Chisel or Yosys. Done means the ownership and a concrete correction path are established.

Written by the indexing model from the issue text.