Make verilog Error

Hi Team,

we installed rocket tools and chisel in machine and set the path, when we run the cmd "make verilog" in rocket-chip we are geeting attached error. Can you help me on this issue please

Start with the rocket-chip setup instructions and the `make verilog` entry point, then inspect the attached error and verify the configured Rocket tools and Chisel paths. Done means the command completes successfully and generates Verilog output; the issue does not include the error text or identify a failing file or test.

Written by the indexing model from the issue text.